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Circuit Switching

  A dedicated communication path is estab nodes of the network 
This path/CAPACITY stays up for the duration of the communication 
 Example is Telephone Network

    Packet Switching  

  No capacity is dedicated alstored briefly and then transmitted to the next
Example is : Computer to Computer Communication
o ong a path through the network
o  Data Is sent out in small chunks called “Packets”
o  Each path is passed from node to node
o  At each node, entire packet is received,node.
  

Frame Relay & ATM ror Protection are removed 
o  Overhead bits for Er
o  10’s of 100’s of Mbps and also Gbps is possible  

WANS

aphical area and it usually span an Unlimited number of

  Design of a WAN
 it consists of a large number of Switching Nodes
Transmission from any one device is routed through these intspecified destination device
These  nodes  are  not  conce
purpose is to provide a switching facility that will move the data from node to
node until it reaches its destination .


o  How to Implement a WAN?
 Traditionally WAN s have been implemented using one of the 2 technologies:  9  Traditionally WAN s
–Circuit Switching
–Packet Switching

Design of a LAN

¾  LANs are designed to allow resources to be shared between personal computers or
¾  s  to  be shared can include hardware (printer), software (an

9  Example of a LAN
 of a LAN  found  in many business environments links a

  Transmission Media & Topology
e distinguished from other types of networks by
9  ly one type of Transmission medium 

workstations
The  resourceapplication program) or data.
A common examplework group of task related computers,  for example engineering workstations or Accounting PCs. One of the PCs may be given a large capacity disk and becomes a server to others.Software stored on the server and is used by the whole group. In this case size is determined by software licenses.

  In addition  to  size, LANs ar
Transmission media and topology In general a given LAN will use on
  The most common LAN topology Bus, Star Ring

Data Rates in a LAN  
 1  Mbps
00Mbps and above are also possible
  Traditionally 4 – 6
  Speeds increased and now 1
  Giga Bit LAN technologies

Categories of Networks

  There are three main categories of Networks:
  LANS
o  Into which category a network falls is determined by its  SIZE, OWNERSHIP,

o

  WANS
  MANS

DISTANCE IT COVERS, and its PHYSICAL ARCHITECTURE
  LANS
o
  Two Implications
  taken in choice of a LAN, because there may be a substantial
  ility  falls  solely  on  the

  Size of a LAN
a  LAN depends upon the Needs  of Organization and the Type of
   LAN can be as simple as two PCs and a printer in someone’s home office or it



A LAN is usually Privately owned and Links the devices in a single office, Building or a campus

Care must be capital investment for purchase and maintenance.
Secondly, the network management responsib
user/company Size  of Technology can extend throughout a company and include complex equipment too Currently LAN size is limited to a few kilometers

Hybrid Topologies

o  Several topologies combined in a larger topology
   Example: One department of a business may have decided to use a Bus while other has a Ring
o  The two can be connected via a Central Controller in Star Topology

TRANSMISSION MODE

“Transmission Mode is used to define the direction of the signal flow between the linked devices”

o  Communication is Unidirectional
o  Only one of the two stations can transmit
o  Other can only receive

  Examples:  KEYBOARDS (Only Input), Monitors (Only Output)

Ring Topology

o  Each device has point-to-point dedicated link with only two devices on either side 
o  A signal is passed in the ring in one direction from device to device until it reaches its
destination
o  Each device has a repeater incorporated
o  When a device receives a signal destined for another device, it regenerates the bits
and pass them along

™ Advantages of Ring Topology

  Easy to Install and Reconfigure
  Only two connections to be moved to add or delete a device

  SIMPLE Fault Isolation
  Generally a signal is circulating at all times in a ring. If one device does not receive a signal within a specified period, it can issue an alarm to tell network operator about the problem and its location
 
™ Disadvantages of Ring Topology

  Unidirectional Traffic 
  A break in a ring I.e. a disabled station can disable the entire network
 Can be solved by using:

BUS TOPOLOGY

o  Drop Lines and Taps
o  Drop Line is the connection between device and the main cable (Backbone)
¾  Tap is a connector that;
Splices into the main cable   or
Punctures the sheathing of a cable to create connection with the
metallic core


  Signal degrades as it travels, therefore there is a limit on:
  The number of Taps a Bus can support and
  The distance between those Taps

™ Advantages of BUS TOPOLOGY

  Easy to install
  Backbone can be laid on the most efficient path and then rest of the nodes can be connected using Drop Lines
  Less cabling than Mesh , Star or Tree
  Difference b/w Star Cabling and Bus Cabling


™  Disadvantages of BUS Topology

  Difficult Reconfiguration
  Difficult to add new devices
   adding new devices may require modification of backbone 

  No Fault Isolation
  A fault or break in backbone can disable communication even on the same side of the problem
  Damaged area reflects signals back in the direction of origin creating Noise in both directions

CENTRAL HUB in Tree Topology

  Central Hub in a Tree is an ACTIVE HUB
  ACTIVE HUB contains a repeater
  Repeater is a hardware device that regenerates the received bit pattern before
sending them out.
  Repeater strengthens TX. And increases the distance a signal can travel

™  Secondary HUB in Tree Topology

  Secondary Hub in a Tree may be Active or  Passive HUB
  Passive Hub simply provides physical connection between attached devices ™  Advantages of Tree Topology

  Because of Secondary Hub, More devices can be attached to a Central Hub
and therefore increase the distance a signal can travel
  Enables Differentiated Services: Allows to prioritize communication, e.g.
computers attached to one secondary hub can be given priority over others
  Therefore, TIME SENSITIVE data will not have to wait for access to the
network
  Rest of the advantages are almost the same as STAR
  Example Tree Topology: Cable TV

CABLE TV
–Main cable from main office is divided into many
branches and each branch is divided into smaller branches and so on 
–Hubs are used when cable is divided

Advantages & Disadvantages of Mesh Topology

™  Advantages of Mesh Topology

  Use of Dedicated links guarantees that each connection can carry its own load.
This eliminates Traffic Problems as in case of Shared Link
  Mesh Topology is robust. If one link fails, it does not effect other links
  Security & Privacy due to dedicated links
  Point – to –Point links make Fault Identification easy

™  Disadvantages of Mesh Topology

  Amount of Cabling
  Makes Installation & Reconfiguration difficult
  Sheer bulk of wiring can be greater than the available space

  Number of I/O Ports Required
  Hardware required to connect each link can be prohibitively expensive
 
o  Each device has a dedicated point-to-point link to a central controller ( Hub)
o  Devices are not directly connected to each other 
o  Controller (Hub) acts as an exchange
o  If one device wants to send data to the other, it sends the data to the controller , which then relays it to the other connected device

TOPOLOGY

“The Topology is the geometric representation of the relationship  of the links and the linking devices (Nodes) in a Network” 
Or
“Topology defines the physical or the Logical Agreement of Links in a Network”

Topology of a Network is suggestive of how a network is laid out. It refers to the specific configuration and structure of the connections between the Links and the Nodes. Two or more devices connect to a Link and two or more Links form a Topology


  Question: What to consider when choosing a Topology????????
  Answer: Relative status of the devices to be linked.

Two relationships are possible in a network

  PEER-TO-PEER: Devices share the link equally

  PRIMARY-SECONDARY: One device controls traffic and the others must transmit through it


o  Every device has dedicated a point-to-point link to every other device
o  Dedicated: Means that the link carries traffic only between these two devices
Links to connect ‘n’ devices
o  Each device must have         
   I/O Ports

Example Mesh Topology
In figure above, we have 5 Nodes, therefore:

  No. of Links= 5(5-1)/2 = 10
  No. of I/O Ports= 5-1 = 4

  This increase exponentially with increase in No. of Nodes

  e.g. for 6 nodes = 15 Links 7 Nodes=21 Links 1 − n 2) 1 ( − n n

LINE CONFIGURATION

“Line Configuration refers to the way two or more devices attach to a Link”

A link is the physical communication path that transfers data from one device to the other. Link can be thought of as a Line drawn between two points. For communication to occur, two devices must be connected to each other using a link.
 
™  Point-to-Point Line Configuration

Dedicated Link between two devices. Entire Capacity of the channel is reserved for TX B/w these two devices. Mostly point-to-point connection use wire/cable to connect with each other. But Microwave, Satellite Links can also be used Data and Control information pas directly between entities with no intervening agent

™  Multipoint Line Configuration
More than two devices share the Link that  is the capacity of the channel is SHARED now. With shared capacity, there can be two possibilities in a Multipoint Line Config:

  Spatial Sharing: If several devices can share the link simultaneously, its called Spatially shared line configuration

  Temporal (Time) Sharing: If users must take turns using the link , then its called Temporally shared or Time Shared Line Configuration

Standard Organizations

Standards are developed mainly by 3 entities:

  Standard Creation Committees 
  Forums
  Regulatory Agencies


™  Standard Creation Committees

They are Procedural Bodies and they are so slow moving and cannot co-op with the fast
growing communication industry. 

  ISO 

  International Standard’s Organization
  Voluntary Organization 
  Created in 1947
  Members are from Standard Creation Committees of different countries
  Includes representatives from 82 countries
  Open System Interconnection (OSI) Model

  ITU-T

  By 1970s a lot of countries were defining standards but there was no
International compatibility
  United Nations made as a part of their ITU
  Consultative Committee for International Telegraphy and Telephony
(CCITT)
  IN 1993 , ITU-Telecomm Standards Sector
  Important ITU-T Standards
  V Series (V32, V33, V42, Define Data Transmission over phone lines
  X Series(X.25, 400, 500): Define Transmission over Public Digital
Network
  ISDN: Integrated Services Digital Network

  The American National Standard Institute (ANSI)

  Private-Non Profit Cooperation not affiliated  with US Government
  Members include professional societies, industrial associations, govt. and regulatory bodies
  Submits proposal to ITU-T and is a voting member for USA in ISO

Characteristics of a Protocol

¾  Direct or indirect
¾  Monolithic or structured
¾  Symmetric or asymmetric
¾  Standard or nonstandard

™  Direct

  Systems share a point to point link or
  Data can pass without intervening active agent
  Simple Protocol

™  Indirect

  Switched networks or
  Interne works or internets
  Data transfer depend on other entities
  Complex Protocol


™  Monolithic or Structured

  Communications is a complex task
  To complex for single unit
  Structured design breaks down problem into smaller units
  Layered structure

™  Symmetric or Asymmetric

Symmetric
  Communication between peer entities

Asymmetric
  Client/server

Introduction to Protocol

In computer Networks, communication occurs between two entities in different systems. 

o  Entity is anything sending and receiving information
o  SYSTEM is a physical object containing more than one entities
 Now, two entities in different systems cannot just send data and expect to be understood.
For communication to occur, these entities must agree on a PROTOCOL

PROTOCOLS
As discussed earlier, “Protocol is a set of rules governing communication”

o  Two computers cannot just send bit streams to each other and expect to be
understood
o  Entities must agree on a PROTOCOL

9  Same Example French and German

Protocol defines:
 What is Communicated?  

How it is Communicated?  

When it is Communicated?


KEY elements of a PROTOCOL
™  Syntax:

  Represents the Structure or the format of the Data
  Meaning the order in which data is presented

For Example
9  First eight bits to be Sender address
9  Next eight to be Receiver’s Address
9  The Rest to be Data

™  Semantics:

  Refer to the Meaning of each section of bits
  How is a particular pattern to be interpreted?
  What action should be taken based on interpretation?

For Example
9  Does an address identify the route to be taken or the final destination of the message?

™  Timing

Refers to 2 characteristics:
When data should be sent?
 How fast it should be sent?

For Example
9  If sender produces data at 100 Mbps
9  But Receiver can only process data at 1 Mbps 
9  The TX. will overload receiver and data will be lost 

Networks- Why we need them?

It is often impractical for devices to be directly connected for two major reasons:

o  The devices are very far apart. They are expensive to connect just two devices
with one in Lahore and other in Islamabad
o  Large set of devices would need impractical number of connections e .g.
Telephone Lines in the world and all the computers owned by a single organization
 Solution to the Problem=Networks

o  Solution is to connect all devices to a central system known as a NETWORK in which all terminals or computers share the links.

o  Two Main Classifications of the Networks

DISTRIBUTED PROCESSING

o  Instead of a single large machine being responsible for all aspects of a process , each separate computer handles a subset of the task
9  Example – Project Given as a part of the Course
9  Example – Office Work 

Advantages of Distributed Processing

™  Security 

A system designer can limit the kind of interaction that a given user can have with the entire system.

  For example :  Bank’s ATM


™  Distributed Data bases

No one system need to provide storage capacity for the entire database

9  For example WWW gives user access  to pages stored anywhere on Internet

™  Faster Problem Solving

Multiple computers working on a problem can solve a problem faster than a computer working alone

™  Security through Redundancy

Multiple computers running the same program provide security through redundancy If one computer hardware breaks down then others cover up.

KEY DATA COMMUNICATION TERMINOLOGY

™  Link: connects adjacent nodes
Wires, Cables, Any thing that physically connects two nodes

™  Path: end-to-end route within a network

™  Circuit: the conduit over which data travels

™  Packetizing: dividing messages into fixed-length packets prior to transmission
over a network’s communication media

™  Routing: determining a message’s path from sending to receiving nodes
  
The transmission medium may itself be a network, so route needs to be specified .
 .

Power: switching and leakage

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nano meter process, switching the output might take 120 picoseconds, and happen once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from V_dd to V_ss through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components:

• Static dissipation

• Sub threshold condition when the transistors are off.
  
  Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current (called sub threshold current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (V_dd might have been 5 V, and V_thfor both NMOS and PMOS might have been 700 mV). A special type of the CMOS transistor with near zero threshold voltage is the native transistor.

• Tunnelling current through gate oxide.
  
  SiO₂ is a very good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.

• Leakage current through reverse biased diodes.
  
  Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

• Contention current in ratioed circuit

• Dynamic Dissipation

• Charging and discharging of load capacitances.
  
  CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from V_DD to the load capacitance to charge it and then flows from the charged load capacitance to ground during discharge. Therefore in one complete charge/discharge cycle, a total of Q=C_LV_DD is thus transferred from V_DD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: .
  
  Since most gates do not operate/switch at every clock cycle, they are often accompanied by a factor , called the activity factor. Now, the dynamic power dissipation may be re-written as .
  
  A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.5. If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

• Short circuit power dissipation
  
  Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from V_DD to ground, hence creating a short circuit current. Short circuit power dissipation increases with rise and fall time of the transistors.
  
  An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS logic networks are partially conductive, and current flows directly from V_dd to V_SS. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power.

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a V_th of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. Multi-threshold CMOS (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high V_th transistors are used when switching speed is not critical, while low V_th transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional leakage component because of current tunnelling through the extremely thin gate dielectric. Using high-k dielectrics instead of silicon dioxide that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.

Logic

More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and V_ss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and V_dd (voltage source), bringing the output high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit.

Duality

An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

Inversion

CMOS circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

The image on the right shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output to drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behaviour of input and output, the CMOS circuits' output is the inverse of the input.

A note on nomenclature:  The power supplies for CMOS are called V_DD and V_SS, or V_CC and Ground(GND) depending on the manufacturer. V_DD and V_SS are carryovers from conventional MOS circuits and stand for the drain and source supplies. These do not apply directly to CMOS since both supplies are really source supplies. V_CC and Ground are carryovers from TTL logic and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

Composition

The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal–oxide–semiconductor field-effect transistors to create paths to the output from either the voltage source or ground. When a path to output is created from the voltage source, the circuit is said to be pulled up. The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential.

Technical details

"CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes. As of 2010, CPUs with the best performance per watt each year have been CMOS static logic since 1976.

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. Although CMOS logic can be implemented with discrete devices (e.g., for instructional purposes in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions of transistors of both types on a rectangular piece of silicon of between 10 and 400mm². These devices are commonly called "chips", although within the industry they are also referred to as a "die" (singular), "dice" (plural), or "dies" (plural).

CMOS

Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers,static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integratedtransceivers for many types of communication. Frank Wanlass patented CMOS in 1967 (US patent 3,356,858).

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or COS-MOS).^[1] The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type andn-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as muchwaste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminium was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometre node and beyond.

Core i7

The Core i7 brand remains the high-end for Intel's desktop and mobile processors, featuring the Sandy Bridge models with the largest amount of L3 cache and the highest clock frequency. Most of these models are very similar to their smaller Core i5 siblings. The quad-core mobile Core i7-2xxxQM/XM processors follow the previous "Clarksfield" Core i7-xxxQM/XM processors, but now also include integrated graphics.

Codename (main article)	Brand name (list)	Cores	L3 Cache	Socket	TDP	Process	I/O Bus	Release Date
Sandy Bridge-E (Desktop)	Core i7-3960X	6	15 MB	LGA 2011	130 W	32 nm	Direct Media Interface	November 2011
	Core i7-3930K		12 MB
	Core i7-3820	4	10 MB					November 2011
Sandy Bridge (Desktop)	Core i7-2600, 2600K, 2700K	4	8 MB	LGA 1155	95 W		Direct Media Interface, Integrated GPU	January 2011
	Core i7-2xxxS				65 W
Sandy Bridge (Mobile)	Core i7-2xxxXM	4	8 MB	rPGA-988B BGA-1023	55 W			January 2011
	Core i7-2xxxQM		6 or 8 MB		45 W
	Core i7-2xxxQE		6 MB		45 W
	Core i7-2xx0M	2	4 MB	rPGA-988B BGA-1023	35 W			February 2011
	Core i7-2xx9M			BGA-1023	25 W
	Core i7-2xx7M				17 W

Core i5

January 2011, Intel released new quad-core Core i5 processors based on the "Sandy Bridge" microarchitecture at CES 2011. New dual-core mobile processors and desktop processors arrived in February 2011.

The Core i5-2xxx line of desktop processors are mostly quad-core chips, with the exception of the dual-core Core i5-2390T, and include integrated graphics, combining the key features of the earlier Core i5-6xx and Core i5-7xx lines. The suffix after the four-digit model number designates unlocked multiplier (K), low-power (S) and ultra-low-power (T). The desktop CPUs now all have four non-SMT cores (like the i5-750), with the exception of the i5-2390T. The DMI bus is running at 5 GT/s.

The mobile Core i5-2xxxM processors are all dual-core chips like the previous Core i5-5xxM series and share most the features with that product line.

Codename (main article)	Brand name (list)	Cores	L3 Cache	Socket	TDP	I/O Bus
Sandy Bridge (Desktop)	Core i5-2xxx Core i5-2xxxK	4	6 MB	LGA 1155	95 W	Direct Media Interface, Integrated GPU
	Core i5-2xxxS			LGA 1155	65 W	Direct Media Interface, Integrated GPU
	Core i5-2xxxT	2-4			35-45 W	Direct Media Interface, Integrated GPU
Sandy Bridge (Mobile)	Core i5-2xxxM	2	3 MB	rPGA-988B BGA-1023	35 W	Direct Media Interface, Integrated GPU
	Core i5-2xx7M			BGA-1023	17 W	Direct Media Interface, Integrated GPU